The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
The density of solid-state memory devices is increasing as more bits of user data can be stored into each solid-state storage element. For example, flash memory devices may store two bits per storage element by varying the stored charge in the storage element to one of four (22) levels in order to produce one of four threshold voltages. Currently, storing even more bits (such as three or four) per storage element is being investigated.
Other solid-state storage elements, such as those used in phase-change memory (PCM) devices, may store data as varying levels of resistance. Regardless of the storage mechanism, optimum spacing of the different levels may take into account the uncertainty of writing and/or reading each level. For example, within the range of achievable levels, two or more predefined levels may be established. The term level may include a voltage, a current, a resistance, or any other suitable storage parameter. The range of achievable levels is defined by a lower limit and an upper limit, which may be governed by process parameters. To write data, the storage element is programmed to one of the predefined levels. To read data, the level of the storage element is compared to the predefined levels.
There may be variability or uncertainty in reading or writing the level of a storage element. For example, when writing a first predefined level, the actual level achieved may be slightly above or below the first predefined level. This may be the result of, for example, programming the storage element using an open-loop process that is not calibrated perfectly. Alternatively, even if a closed-loop process is used, the first predefined level may be overshot or undershot. For example, this may occur when, during the last programming iteration, the programming granularity is greater than the difference between the current level and the first predefined level.
In addition, even if the first predefined level is written precisely, the level read may not be exactly equal to the first predefined level. For example, the level of the storage element may decay or shift with time. In addition, noise, crosstalk, and/or uncertainty in the reading process may lead to a slightly different level being read. A probability density function may be defined that represents the likelihood of a certain level being read a predetermined time after a predefined level is written.
FIG. 1 is a graphical representation of exemplary probability density functions (pdfs) for a four-predefined-level write scheme. In this example, the four predefined levels, L0, L1, L2, and L3, have corresponding pdfs with approximately the same shape. For example, when predefined level L0 is written, FIG. 1 indicates that the actual level achieved is most likely L0. However, it is only slightly less likely that the level achieved is slightly above or below L0. The probability of a resulting level decreases as it gets further from L0.
It may be desirable to space the predefined levels so that each pdf ends (drops to zero) before the next pdf begins, as shown in FIG. 1. For example, this may ensure that a level on the high side of the level L1 pdf is not misinterpreted as a level on the low side of the level L2 pdf. The predefined levels L0, L1, L2, and L3 may therefore be arranged so that their pdfs do not overlap. When the pdfs for various levels are approximately the same, the predefined levels may be uniformly spaced to achieve this goal.
FIG. 2 depicts exemplary pdfs for a four-predefined-level write scheme when the pdfs differ. For example, in FIG. 2, the L0 pdf is wider (has a greater standard deviation) than that of L1, L2, and L3. There are various reasons why pdfs may be different for different levels. For example, L0 may be an erased level, which cannot be controlled as accurately as programmed levels. Other process variability or design considerations may affect the size and shape of the pdfs.
To accommodate the widened level L0 pdf, predefined levels L1 and L2 may be moved slightly higher and closer to each other, as shown in the example of FIG. 2. As more levels are introduced, the proximity of the pdfs may increase, and it may not be possible to avoid overlap between the pdfs. Error control coding may be used, which may identify and/or correct errors resulting from misreading of a previously written level.
Referring now to FIG. 3, a functional block diagram of a memory system according to the prior art is presented. A memory controller 100 interfaces with a memory chip 102. For a write, the memory controller 100 sends user data to the memory chip 102 along with an address to which the user data should be written. The memory controller 100 may also indicate to the memory chip 102 that a write is desired using a read/write signal. The memory chip 102 converts the user data into predefined levels for each storage element that will be written. The memory chip 102 then writes the predefined levels to the storage elements at the designated address.
During a read, the memory controller 100 requests a read from the memory chip 102 and provides an address. The memory chip 102 measures the levels of the storage elements at the given address. These levels are matched up with the closest predefined levels, which are then mapped back to user data. The user data is returned to the memory controller 100. For example, with reference to FIG. 2, if a threshold voltage slightly above predefined level L3 is measured from a charge storage cell, the memory chip 102 decides that predefined level L3 had previously been written.
Predefined level L3 may correspond to a bit pattern of 11, which the memory chip 102 then returns to the memory controller 100. The values of the predefined levels and data/level mappings are determined at design time and hard coded into the memory chip 102. The memory controller 100 does not need to be aware of any level information, simply transmitting binary user data to the memory chip 102 and receiving binary user data from the memory chip 102.